With continuous progress of very-large-scale integration (VLSI) technology, the feature size of semiconductor structure is continuously shrinking, the chip area is persistently getting bigger, and the delay time of interconnect structure is now comparable to the delay time of device gate. People are facing a problem of how to overcome RC (R means resistance while C refers to the capacitance) delay due to the rapid increase of the length of the connections. In particular, the growing influence of the line capacitance between metal wires has resulted in a significant decline in device performance, and thus has become a key constraint to the further development of the semiconductor industry. A number of measures have been adopted to reduce the RC delay caused by interconnections.
Parasitic capacitance and interconnect resistance between interconnect structures cause transmission delay of the signal. Because copper has relatively low resistivity, excellent anti-electromigration characteristics, and high reliability, it can be used to reduce interconnect resistance of metals, thus further reduce the total interconnect delay effect. Therefore, in semiconductor structures, the conventional aluminum interconnect has been replaced by low-resistance copper interconnect. In the meantime, reducing interconnect capacitance may also reduce the delay. Since the parasitic capacitance C is proportional to the relative dielectric constant k of the insulating dielectric material in a circuit layer, using low-k dielectric materials or ultra-low-k dielectric materials as insulating dielectric of different circuit layers to replace the traditional SiO2 dielectric has become a prerequisite to meet with the development of high-speed chip.
However, the performance of semiconductor structures containing interconnect structures formed by the current technology still needs to be further improved. The disclosed semiconductor structure and fabricating process are directed to solve one or more problems set forth above and other problems.